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SIT5156 1 to 60 mhz, 0.5 ppm elite platform? super - tcxo preliminary description the SIT5156 is a 0.5 to 2.5 ppm mems super - tcxo engineered for best dynamic performance. it is ideal for high reliability telecom, wireless and networking , indust rial, precision gnss and audio/video applications. by l everaging sitime s unique dualmems? temperature sensing and turbocompensation? technology , th e SIT5156 deliver s the most stable t iming in the presence of environmental stressors C air flow, temperatu re perturbation, vibrat ion, shock and electromagnetic interference (emi). this device also integrates multiple on - chip regulators , providing power supply noise fil tering and eliminating the need for a dedicated external ldo. the SIT5156 offers three device configurations that can be ordered with the associated ordering c odes : 1) tcxo with non - pullable output frequency 2) v ctcxo allowing volta ge control of output frequency 3) dctcxo enabling digital control of the output frequency thro ugh the i 2 c interface SIT5156 can be factory - programmed to any combination of frequency, stability, voltage, and pull range. this programmability enables designers to optimize the clock configuration while eliminating the long lead time and customizat ion cost associated with quartz tcxos where each frequency is custom built . refer to manufacturing g uideline for proper reflow profile and pcb cleaning recommendations to ensure best performance. feature s ? any fr equency between 1 mhz and 60 mhz in 1 hz step s ? excellent dynamic stability under airflow and rapid temperature change ? 5 00 ppb over - temperature stability ? 1 5 ppb/ ? c frequency slope (f/t) ? 3e - 11 adev at 10 second averaging time ? - 40c to + 105 c o perating temperature ? no activity dips or micro jumps ? resistant to shock, vibration and board bending ? up to 3200 ppm pull range (vctcxo or dctcxo) ? d igital frequency pulling (d ctcxo ) via i 2 c ? digital control of output frequency and pull range ? frequenc y pu ll reso lution as low as 5 ppt (0.0 0 5 ppb ) ? 2.5 v , 2.8v, 3.0 v and 3.3 v supply voltage ? on - chip regulators, eliminating the need for the external ldo ? lvcmos or clipped sinewave output ? rohs and reach compliant, pb - free, halogen - free and antimony - free applicatio ns ? precision gnss ? microwave backhaul ? network switches and routers ? professional audio and video equipment ? storage and servers ? test and measurement block diagram figure 1 . SIT5156 block diagram 5.0 x 3.2 mm package pinout figure 2 . pin assignments (top view) ( r efer to table 9 for pin descriptions) rev 0. 60 march 1, 2018 www.sitime.com o e / v c / n c 1 2 3 4 5 6 7 8 9 1 0 s c l / n c n c g n d n c n c v d d c l k a 0 / n c s d a / n c
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 2 of 36 www.sitime.com table of contents description ................................ ................................ ................................ ................................ ................................ ................... 1 features ................................ ................................ ................................ ................................ ................................ ....................... 1 applications ................................ ................................ ................................ ................................ ................................ ................. 1 block diagram ................................ ................................ ................................ ................................ ................................ ............. 1 electrical characteristics ................................ ................................ ................................ ................................ .............................. 3 modes of operation and pin - outs ................................ ................................ ................................ ................................ ................ 6 pin - out top views ................................ ................................ ................................ ................................ ................................ . 6 test circuit diagrams for lvcmos and clipped sinewave outputs ................................ ................................ ........................... 7 waveforms ................................ ................................ ................................ ................................ ................................ ................... 9 timing diagrams ................................ ................................ ................................ ................................ ................................ ........ 10 architecture & functional overview ................................ ................................ ................................ ................................ ........... 11 frequency stability ................................ ................................ ................................ ................................ ............................. 11 out put frequency and format ................................ ................................ ................................ ................................ .............. 11 output frequency tuning ................................ ................................ ................................ ................................ ................... 11 pin 1 configuration (oe, vc, or nc) ................................ ................................ ................................ ................................ .. 12 operating mode descriptions ................................ ................................ ................................ ................................ .................... 13 tcxo mode ................................ ................................ ................................ ................................ ................................ ........ 13 vctcxo mode ................................ ................................ ................................ ................................ ................................ ... 14 linearity ................................ ................................ ................................ ................................ ................................ .............. 15 control voltage bandwidth ................................ ................................ ................................ ................................ ................. 15 fv characteristic slope k v ................................ ................................ ................................ ................................ ................. 15 dctcxo mode ................................ ................................ ................................ ................................ ................................ ... 16 pull range, absolute pull range ................................ ................................ ................................ ................................ ............... 16 i 2 c control registers ................................ ................................ ................................ ................................ ................................ . 21 register descriptions ................................ ................................ ................................ ................................ ................................ . 21 register address: 0x00. digital frequency control least significant word (lsw) ................................ ............................ 21 register address: 0x01. oe control, digital frequency control most significant word (msw) ................................ ......... 22 register address: 0x02. digital pull range control ................................ ................................ ............................ 23 register address: 0x05. pull - up drive strength control ................................ ................................ .................. 24 register address: 0x06. pull - down drive strength control ................................ ................................ ............ 25 serial interface configuration description ................................ ................................ ................................ ................................ .. 26 serial signal format ................................ ................................ ................................ ................................ ................................ .. 26 parallel signal format ................................ ................................ ................................ ................................ ................................ 27 parallel data format ................................ ................................ ................................ ................................ ................................ .. 27 i 2 c timing specification ................................ ................................ ................................ ................................ ............................. 29 i 2 c device address modes ................................ ................................ ................................ ................................ ........................ 30 schematic example ................................ ................................ ................................ ................................ ................................ ... 3 1 dimensions and patterns ................................ ................................ ................................ ................................ ........................... 32 layout guidelines ................................ ................................ ................................ ................................ ................................ ...... 33 ordering information ................................ ................................ ................................ ................................ ................................ .. 34
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 3 of 36 www.sitime.com electrica l characteristics all min and max limits are specified over temperature and rated operating voltage with 15 pf o utput load unless otherwise stated. typical values are at 25c and 3.3v vdd table 1 . output c haracteristics parameters symbol min. typ. max. unit condition frequency coverage output frequency range f 1 C 60 mhz lvcmos output 1 C 50 mhz clipped sinewave output lvcmos output characteristics duty cycle dc 45 C 55 % rise/fall time tr, t f C 1 C ns 10% - 90% vdd output voltage high voh 90% C C vdd i oh = - 6 ma, ( vdd = 3.3 v, 3.0 v, 2.8 v, 2.5 v) output voltage low vol C C 10% v dd i ol = 6 ma, ( vdd = 3.3 v, 3.0 v, 2.8 v, 2.5 v) clipped sinewave output characteristics output voltage level v_out 0.8 C 1.2 v measured peak - to - peak swing at any vdd frequency stability - stratum 3 grade frequency stability over temperature f_stab - 0 .5 C +0.5 p pm referenced to (f max + f min )/2 over the specified temperature range see ordering information for frequency stability ordering codes (k, a, d) - 1.0 C +1.0 ppm - 2.5 C +2.5 p pm frequency vs. temperature slope f/ t C 15 C ppb/c f_stab = 0.5 ppm C 25 C ppb/c f_stab = 1 ppm C 60 C ppb/c f_stab = 2.5 ppm dynamic frequency change during temperature ramp f_dynamic C 0.13 C ppb/s f_stab = 0.5 ppm , 0.5 ? c/min temperature ramp rate C 0.21 C ppb/s f_stab = 1 .0 ppm , 0.5 ? c/ min temperature ramp rate C 0.5 C ppb/s f_stab = 2.5 ppm , 0.5 ? c/ min temperature ramp rate initial tolerance f_init - 1 C +1 ppm initial frequency at 25c inclusive of solder - down shift at 48 hours after 2 reflows supply vo ltage sensitivity f_vdd C 20 C p pb vdd 5% output load sensitivity f_load C 1 0 C p pb lvcmos output, 15 pf 10% C 1 0 C p pb clipped sinewave output, 10k?, 10 pf 10% first year aging f_1y C 1 C ppm at 25 c start - up characteristics start - up time t_start C 5 C ms time to first pulse, measured from the time vdd reaches 90% of its final value first pulse accuracy t_stability C 10 C ms time to first accurate pulse within rated stability , measured from the time vdd reaches 90% of its final value
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 4 of 36 www.sitime.com table 2 . dc characteristics parameters symbol min. typ. max. unit condition supply voltage supply voltage v dd 2.25 2.5 2.75 v contact sitime for 2.25v to 3.63v continuous supply voltage support 2.52 2.8 3.08 v 2.7 3.0 3.3 v 2.97 3.3 3.63 v current consumption current consumption idd C 40.5 C ma f = 19.2 mhz, no load oe disable current i_od C 40 C ma oe = gnd, output is weakly pulled down temperature range operating temperature range t_use - 20 C +70 c extended c ommercial - 40 C +85 c industrial. contact sitime for 105 c support - 40 C +105 c extended industrial table 3 . input characteristics parameters symbol min. typ. max. unit condition input characteristics C oe pin input impedance z_in C 100 C k? i nternal pull up to vdd input high voltage vih 70 C C % input low voltage vil C C 30 % frequency tuning range C voltage control or i 2 c mode pull range pr 6.25, 10, 12.5, 25 , 50, 80, 100, 125, 150, 200, 400, 600, 800, 1200, 1600, 32 00 p pm voltage control characteristics upper control voltage vc_u 90% C C vdd lower control voltage vc_l C C 10% vdd control voltage input impedance vc_z 10 C C m ? control voltage input bandwidth vc_c C 10 C khz contact sitime for other input bandwidth options frequency change polarity positive pull range linearity C 0.5 C % i 2 c interface characteristics, 1 mhz, 200 ohm, 550 pf (max i 2 c bus load) input voltage low vil C C 0.3 v inp ut voltage high vih 0.7 C C v output voltage low vol C C 0.4 v output current high iol 21 C C ma leakage in high impedance mode i_leak 5.5 C 24 a 0.1 vdd < vout < 0.9 vdd input hysteresis v_hys 0.2 C 0.4 v vdd = 3.3v 0.2 C 0.3 v vdd = 2.5v input capacitance c_in C C 3 pf rise time tr C C 120 ns fall time tf 30 C 60 ns vdd = 3.3v, 30% to 70% 40 C 75 ns vdd = 2.5v, 30% to 70%
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 5 of 36 www.sitime.com table 4 . jitter & phase noise parameters symbol min. typ. max. unit condition jitter rms phase jitter (random) t_phj C 0.35 C ps f = 10 mhz, integration bandwidth = 12 khz to 5 mhz C 0.33 C ps f = 50 mhz, inte gration bandwidth = 12 khz to 20 mhz spurs C - 104 C dbc f = 10 mhz, 12 khz to 5 mhz offsets rms period jitter t_jitt C 2 C ps f = 10 mhz per jesd65 standard peak cycle - to - cycle jitter t_jitt_cc C 10 C ps f = 10 mhz per jesd65 standard phase noise 1 hz offset C - 70 C dbc/hz f = 10 mhz , tcxo and dctcxo modes, and vctcxo mode with 6.25 ppm pull range 10 hz offset C - 100 C db c/hz 100 hz offset C - 130 C dbc/hz 1 khz offset C - 145 C dbc/hz 10 khz offset C - 152 C dbc/hz 100 khz offset C - 155 C dbc/hz 1 mhz offset C - 162 C dbc/hz 5 mhz offset C - 165 C dbc/hz table 5 . absolute maximum li mits attempted operation outside the absolute maximum ratings may caus e permanent damage to the part. actual performance of the ic is only guaranteed within the operational specifications, not at absolute maximum ratings. parameter test conditions value un it storage temperature - 65 to 125 c continuous power supply voltage range (vdd) - 0.5 to 4 v human body model (hbm) esd protection jesd22 - a114 C v soldering temperature (follow standard pb - free soldering guidelines) 260 c junction temperature [ 1 ] 130 c note: 1. exceeding this temperature for an extended period of time may damage the device. table 6 . thermal considerations [ 2 ] package ? ja (c/w) ? jc, bottom (c/w) ceramic 5.0 x 3.2 mm 54 15 note: 2. measured in still air. table 7 . environmental compliance parameter test conditions value unit mechanical shock resistance mil - std - 883f, method 2002 20 , 000 g mechanic al vibration resistance mil - std - 883f, method 2007 70 g temperature cycle jesd22, method a104 C C solderability mil - std - 883f, method 2003 C C moisture sensitivity level msl1 @260c C C
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 6 of 36 www.sitime.com device configurations and pin - outs table 8 . device configurations configuration pin 1 pin 5 i 2 c function i 2 c programmable parameters tcxo oe/nc nc no n/a vctcxo vc nc no n/a dctcxo oe/nc a0 /nc yes frequency pull range, frequency pull value, output enable control pin - out top views figure 3 . tcxo figure 4 . vctcxo figure 5 . dctcxo table 9 . pin description pin s ymbol i/o internal pull - up/pull down resistor function 1 oe/nc/vc oe C input 100 k? pull - up h [3 ] : specified frequency output l: output is high impedance. only output driver is disabled nc C no connect - h or l or open: no effect on output frequency or other device functions vc C input - control voltage in vctcxo mode 2 scl/nc scl - input 200 k? pull - up i 2 c serial clock input for dctcxo option. nc fo r tcxo and vctcxo options. nc C no connect - h or l or open: no effect on output frequency or other device functions 3 nc no connect - h or l or open: no effect on output frequency or other device functions 4 gnd power - connect to ground 5 a0 /nc a0 C input 100 k? pull - up device i 2 c address when the addr ess selection mode is via the a0 pin. this pin is nc when the i 2 c device address is specified in the ordering code. a0 logic lev e l i 2 c address 0 1100010 1 1101010 nc C no connect - h or l or open: no effect on output frequency or other device functions 6 clk output - lvcmos or clipped sinewave oscillator output 7 nc no connect - h or l or open: no effect on output frequency or other device functions 8 nc no connect - h or l or open: no effect on output frequency or other device functions 9 vdd power - connect to vdd [4 ] 10 sda/nc sda C input/output 200 k? pull - up i 2 c serial data for dctcxo option. nc for tcxo and vctcxo options. nc - no connect - h or l or open: no effect on output frequency or other device functions notes: 3. in oe mode, a pull - up resistor of 10 k or less is recommended if pin 1 is not externally driven. if pin 1 needs to be left floating, use the nc option. 4. 0.1 f capacitor in parallel with a 10 f capacitor are required between vdd and gnd. o e / n c 1 2 3 4 5 6 7 8 9 1 0 n c n c g n d n c n c v d d c l k n c n c v c 1 2 3 4 5 6 7 8 9 1 0 n c n c g n d n c n c v d d c l k n c n c o e / n c 1 2 3 4 5 6 7 8 9 1 0 s c l n c g n d n c n c v d d c l k a 0 s d a
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 7 of 36 www.sitime.com test circuit diagrams for lvcmos and clipped sinewave outputs figure 6 . lv cmos test circuit (oe function) figure 7 . clipped sinewave test circuit (oe function) figure 8 . lvcmos test circuit (v c function) figure 9 . clipped sinewave test circuit (vc function) figure 10 . lvcmos test circuit (nc function) figure 11 . clipped sinewave test circuit (nc function) 9 8 7 6 1 2 3 4 5 1 0 p o w e r s u p p l y 1 k v d d t e s t p o i n t v d d o e f u n c t i o n c l k 1 5 p f ( i n c l u d i n g p r o b e a n d f i x t u r e c a p a c i t a n c e ) 1 0 f 0 . 1 f + - 1 0 f 0 . 1 f 9 8 7 6 1 2 3 4 5 1 0 p o w e r s u p p l y v d d c l k t e s t p o i n t v d d o e f u n c t i o n 1 0 k ( i n c l u d i n g p r o b e a n d f i x t u r e r e s i s t a n c e a n d c a p a c i t a n c e ) 1 0 p f 1 k + - 1 0 f 0 . 1 f + - 9 8 7 6 1 2 3 4 5 1 0 p o w e r s u p p l y v d d t e s t p o i n t c o n t r o l v o l t a g e v c f u n c t i o n c l k 1 5 p f ( i n c l u d i n g p r o b e a n d f i x t u r e c a p a c i t a n c e ) 9 8 7 6 2 3 4 5 1 0 p o w e r s u p p l y v d d c l k t e s t p o i n t 1 c o n t r o l v o l t a g e v c f u n c t i o n 1 0 k ( i n c l u d i n g p r o b e a n d f i x t u r e r e s i s t a n c e a n d c a p a c i t a n c e ) 1 0 p f 1 0 f 0 . 1 f + - 9 8 7 6 1 2 3 4 5 1 0 p o w e r s u p p l y v d d t e s t p o i n t a n y s t a t e o r f l o a t i n g n c f u n c t i o n c l k 1 5 p f ( i n c l u d i n g p r o b e a n d f i x t u r e c a p a c i t a n c e ) 1 0 f 0 . 1 f + - 9 8 7 6 2 3 4 5 1 0 p o w e r s u p p l y v d d c l k t e s t p o i n t 1 0 p f 1 a n y s t a t e o r f l o a t i n g n c f u n c t i o n 1 0 k ( i n c l u d i n g p r o b e a n d f i x t u r e r e s i s t a n c e a n d c a p a c i t a n c e ) 1 0 f 0 . 1 f + -
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 8 of 36 www.sitime.com figure 12 . lvcmos test circuit ( i 2 c control ) figure 13 . clippe d sinewave test circuit ( i 2 c con trol ) 9 8 7 6 1 2 3 4 5 1 0 p o w e r s u p p l y v d d t e s t p o i n t a n y s t a t e o r f l o a t i n g n c f u n c t i o n c l k s c l s d a 1 5 p f ( i n c l u d i n g p r o b e a n d f i x t u r e c a p a c i t a n c e ) 1 0 f 0 . 1 f + - 9 8 7 6 1 2 3 4 5 1 0 p o w e r s u p p l y v d d t e s t p o i n t a n y s t a t e o r f l o a t i n g n c f u n c t i o n c l k s c l s d a 1 0 p f 1 0 k ( i n c l u d i n g p r o b e a n d f i x t u r e r e s i s t a n c e a n d c a p a c i t a n c e ) 1 0 f 0 . 1 f + -
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 9 of 36 www.sitime.com waveforms [ 5 ] figure 14 . lvcmos waveform diagram figure 15 . clipped sinewave waveform diagram notes 5. duty c ycle is computed as duty cycle = th/period. 9 0 % v d d 5 0 % v d d 1 0 % v d d t r t f h i g h p u l s e ( t h ) l o w p u l s e ( t l ) p e r i o d t r t f h i g h p u l s e ( t h ) l o w p u l s e ( t l ) p e r i o d 2 0 % v o u t 5 0 % v o u t 8 0 % v o u t v o u t
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 10 of 36 www.sitime.com timing di agrams figure 16 . startup timing (oe mode) figure 17 . oe enable timing (oe mode only) figure 18 . oe disable timing (oe mode only) 9 0 % v d d v d d v d d p i n v o l t a g e c l k o u t p u t t _ s t a r t t _ s t a r t : t i m e t o s t a r t f r o m p o w e r - o f f n o g l i t c h d u r i n g s t a r t u p h z 5 0 % v d d v d d o e v o l t a g e c l k o u t p u t t _ o e t _ o e : t i m e t o r e - e n a b l e t h e c l o c k o u t p u t h z 5 0 % v d d v d d o e v o l t a g e c l k o u t p u t t _ o e : t i m e t o p u t t h e o u t p u t i n h i g h z m o d e h z t _ o e
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 11 of 36 www.sitime.com architecture overview based on sitime s innovative elite platform ?, the SIT5156 deliver s e xceptional dynamic performance, i.e. resilience to environmental stressors such as shock, vibration an d fast temperatur e transients. underpinning the elite platform are sitimes unique dualmems ? temperature sensing arc hitecture and turbocompensation ? technology. dualmems is a noiseless temperature sensing scheme. it consists of two mems resonators fabricated on the same d ie substrate. the tempflat ? resonator is designed with a flat frequency characteristic over temperature whereas the temperature sensing resonator is by design sensitive to temperature changes. the ratio of frequencies between these two resonators provides an accurate reading of the resonator temperature with 30 k resolution. by placing the two mems resonators on the same die, this temperature sensing scheme eliminate s the thermal lag and gradients between the resonator and the temperature sensor, an inhere nt weak ness of legacy quartz tcxos. the dualmems temperature sensor is then combined with a state - of - the - art temperature compensation circuit in the cmos ic. the turbocompensation design, with >100 hz compensation bandwidth , achieves dynamic frequency stab ility that is far superior to any quartz tcxo. the 7 th order compensation polynomial enables additional optimization of frequency stability and frequency slope over temperature within any specific temperature range of choice for a given system design . fi gure 19 . elite architecture the elite platform also incorporates a high resolution, low noise frequency synthesizer along with the industry standard i 2 c bus. this unique combination enables system designers to digitally control th e output fr equency in steps as low as 5 ppt (parts per trillion) and over a wide range up to 3200 ppm. f or more information regarding the elite platform and its benefits p lease visit : ? sitime's b reakthroughs section ? tec h p aper: dualmems temperature se nsing te chn ology ? tec hp a per: dualmems resonator tdc functional overview the SIT5156 is designed for maximum flexibility with an array of factory programmable options, enabling system designers to configure this precision device for optimal performance in a given application. frequency stability the SIT5156 comes in three factory - trimmed sta bility grades, each of which is associated with a specific f/ t. the lower f/ t ensures better immunity to air flow and rapid temperature changes. table 10 . stability grades vs. ordering code s frequency stability over temperature frequency slope (f/t) ordering code 0.5 ppm 15 ppb/ ? c k 1 ppm 25 ppb/ ? c a 2.5 ppm 60 ppb/ ? c d output frequency and format the SIT5156 can be programmable for any output frequency from 1 mhz to 60 mhz in steps of 1 hz without sacrificing lead time or incurring upfront customization cost typically asso ciated with custom frequency quartz tcxo. the device supports both lvcmos and clipped sinewave output. o rdering codes for the output format are shown below : table 11 . output formats vs. ordering codes output format ordering code lv cmos - clipped sinewave c output frequency tuning in addition to the non - pullable tcxo, the SIT5156 can also support output frequency tuning through either an analog control voltage (vctcxo) or i 2 c (dctcxo). sixteen pull range options from 6.25 ppm to 3200 ppm are supported in both vctcxo and dctcxo configurations . the dctcxo is recommended to ensure the best phase noise for pull range of 12.5 ppm or above . it also eliminates any sensitivity to the voltage control line noise in a typical vctcxo im plementation, therefore simplifying board level design and layout. in the dctcxo configuration , a user can either specify a desired i 2 c bus address via the appropriate order code, or choose a pre - configured address with pull up/pull down resistors on the a 0 pin (pin 5). the pull rang e can also be reprogrammed via i 2 c to any supported pull range option.
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 12 of 36 www.sitime.com pin 1 configuration (oe, vc, or nc) pin 1 of the SIT5156 can be factory - programmed to support three modes: output enabl e (oe), voltage control (vc) or no co nnect (nc). table 12 . pin configuration options pin 1 configuration operating mode output oe tcxo active or high - z nc tcxo/dc tc xo active vc vctcxo active when pin 1 configured as oe pin, the device output is guaranteed to opera te in one of the following two states: ? at the frequency specified in the part number when pin 1 is pulled to logic high ? in hi - z mode with weak pull down when pin 1 is pulled to logic low. ? no connect (nc) mode when pin 1 is nc, the device is guaranteed t o output the frequency specified in the part number at all times, regardless of the logic level on pin 1. in the vc tcxo configuration , the user can fine - tune the output frequency from the nominal frequency specified in the part number by varying pin 1 vol tage. the guaranteed allowable variation of the output frequency is specified as pull range. a vctcxo part number must contain a valid pull range ordering code.
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 13 of 36 www.sitime.com device configuration s and design considerations the SIT5156 supports 3 device configurations C tcxo, vctcxo and dctcxo. the tcxo and vctcxo options are directly compatible with the quartz tcxo and vctcxo. the d ctcxo configuration provides performance enhancement by eliminating vctcxos sensitivity to control voltage noise with an i 2 c digital interf ace for frequency tuning. figure 20 . block diagram - tcxo tcxo configuration i n the tcxo configuration , the device generate s a fixed frequency output . the frequency is specified by the user in the frequency field of the devi ce ordering code and factory - programmed. other factory programmable options include supply voltage, output types (lvcmos or clipped sinewave) and pin 1 functionality (oe or nc) r efer to the ordering i nformation section at the end of the datasheet for a list of all ordering options. figure 21 . top view C tcxo o e / n c 1 2 3 4 5 6 7 8 9 1 0 n c n c g n d n c n c v d d c l k n c n c
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 14 of 36 www.sitime.com vctcxo configuration vc tc xo is a frequency control device whose o utput frequency is an approximately linear function of control voltage applied to the voltage control pin, vctcxos have a number of use cases including the vco portion of a jitter attenuation/jitter cleaner pll loop. the SIT5156 vctcxo has several inherent advantages over quartz vc tcxos : 1) <0.5% f requency p ull l inearity vs 5% to 10% typical of quartz vctcxos. 2) widest pull range with 16 options: 6.25ppm, 10 ppm, 12.5 ppm, 25 ppm , 50 ppm, 80 ppm, 100 ppm, 125 ppm , 150 ppm, 200 ppm, 400 ppm, 600 ppm , 800 ppm , 1200 ppm, 1600 ppm, 3200 ppm vs. 5 ppm pull range from quartz vctcxos . the SIT5156 achieves 10x better linearity and more pull range options via the fractional feedback divider of the pll rather than pulling the resonator. quartz based vctc xos by contras t changes output f requency by varying the capacitive load of the crystal resonator with varactor diodes, resulting in poor li nearity and limited pull ranges. figure 22 . block diagram - vctcxo note that the outp ut frequency of the vctcxo is proportional to the analog control voltage applied to pin 1. because this control signal is analog and directly controls the output frequency, care must be taken to minimize noise on this pin. the nominal output frequency is f actory programmed per the customers request to 6 digits of precision and is defined as the output frequency when the control voltage equals vdd /2. the maximum output frequency variation from this nominal value is set by the pull range which is also factor y programmed to the customers desired value and specified by the ordering code. the ordering i nformation section shows all the ordering options and associated ordering codes. figure 23 . top view - vctcx o v c 1 2 3 4 5 6 7 8 9 1 0 n c n c g n d n c n c v d d c l k n c n c
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 15 of 36 www.sitime.com linearity in any vctcxo, there will be some deviation of the fv characteristic from an ideal straight line. linearity is the ratio of this maximum deviation to the total pul l range, expressed as a percentage. figure 24 below shows the typical pull linearity of a sitime vctcxo. the linearity is very high relative to most quartz offerings because the frequency pulling is achieved with t he pll rather than varactor diodes used in quartz and is 0.5 % maximum . figure 24 . typical sitime vctcxo linearity fv characteristic slope k v the slope of the fv characteristic is a critical design p arameter in many low bandwidth pll applications. the slope is the derivative of the fv characteristic C the deviation of frequency divided by the control voltage change needed to produce that frequency deviation, over a small voltage span, as shown below: it is typically expressed in khz/ v olt, mhz/ v olt, ppm / v olt, or similar units. slope is usually called k v based on terminology used in pll designs. the extreme linear characteristic of the sitime SIT5156 vctcxo family means that ther e is very little k v variation across the whole input voltage range (typically <1%), significantly reducing the design burden on the pll designer. figure 25 below illustrates the typical k v variation. figure 25 . typical sitime k v variation control voltage bandwidth control v oltage b andwidth, sometimes called m odulation r ate or m odulation b andwidth, is the rate at which the output frequency can track an input v oltage change. the ratio of the output frequency variation to the input voltage variation, previously denoted by k v , has a low - pass characteristic in most v ct cxos. the modulation rate is defined as the modulation rate for which the k v is reduced by 3 db re lative to k v for dc inputs swept in the same voltage range. for example, a part with a 25 ppm pull range and a 0 - 3v control voltage can be regarded as having an average k v of 16.67 ppm/v (50ppm/3v = 16.67 ppm/v). applying an input of 1.5v dc 0.5v (1.0 v to 2.0v) causes an output frequency change of 16.67 ppm (8.33 ppm). if the control voltage bandwidth is specified as 8 khz, the peak - to - peak value of the output frequency change will be reduced to 16.67 ppm/2 or 11.8 ppm, as the frequency of the contr ol voltage change is increased to 8 khz. i n p u t v o l t a g e r a n g e f r e q e u n c y i n p u t v o l t a g e b e s t s t r a i g h t l i n e f i t t o t a l p u l l r a n g e in out v v f k ? ? ? i n p u t v o l t a g e r a n g e k v i n p u t v o l t a g e k v v a r i e s < 1 % o v e r i n p u t v o l t a g e r a n g e a v e r a g e k v
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 16 of 36 www.sitime.com pull range, absolute pull range pull range (pr) is the amount of frequency deviation that will result from changing the control voltage over its maximum range under nominal conditions. absolute pull range ( apr) i s the guaranteed controllable frequency range over all environmental and aging conditions. effectively, it is the amount of pull range remaining after taking into account frequency stability tolerances over variables such as temperature, power supply volta ge, and aging, i.e.: where is the device frequency stability due to initial tolerance and variations on temperature, power supply, and load. figure 26 s hows a typical s itime vctcxo fv characteristic. the fv characteristic varies with conditions, so that the frequency output at a given input voltage can vary by as much as the specified frequency stability of the vctcxo. for such vctcxos, the frequency stability and apr ar e independent of each other. this allows very wide range of pull options without compromising frequency stability. figure 26 . typical sitime vctcxo fv characteristic the upper and lower control voltages are the specified limits of the input voltage range as shown on figure 26 above. applying voltages beyond the upper and lower voltages do not result in noticeable changes of output frequency. in other words, the f v characteristic of the vctcxo saturates beyond these voltages. figures 1 and 2 show these voltages as lower control voltage (vc_l) a nd upper control voltage (vc_u) . table 13 below shows the pull range and corresp onding apr values for each of the frequency vs. temperature ordering options for both the vctcxo and the dc tc xo which will be described in the next section . table 13 . vctcxo, dcxo pull range, apr options [ 6 ] pull range ordering code device option(s) pull range ppm apr ppm 0.5 ppm option apr ppm 1.0 ppm o ption apr ppm 2.5 ppm option t vctcxo, dctcxo 6.25 2.75 2.25 0.75 r vctcxo, dctcxo 10 6.5 6.0 4.5 q vctcxo, dctcxo 12.5 9.0 8.5 7.0 m vctcxo, dctcxo 25 21.5 21.0 19.5 b vctcxo, dctcxo 50 46.5 46.0 44.5 c vctcxo, dctcxo 80 76.5 76.0 74.5 e vctcxo, dctcxo 100 96.5 96.0 94.5 f vctcxo, dctcxo 125 121.5 121.0 119.5 g vctcxo, dctcxo 150 146.5 146.0 144.5 h vctcxo, dctcxo 200 196.5 196.0 194.5 x vctcxo, dctcxo 400 396.5 396.0 394.5 l vctcxo, dctcxo 600 596 .5 596.0 594.5 y vctcxo, dctcxo 800 796.5 796.0 794.5 s vctcxo, dctcxo 1200 1196.5 1196.0 1194.5 z vctcxo, dctcxo 1600 1596.5 1596.0 1594.5 u vctcxo, dctcxo 3200 3196.5 3196 .0 3194.5 notes: 6. apr includes 1 ppm solder down shift, freq uency stability vs. temperature (0.5 ppm, 1.0 ppm, 2.5 ppm) and 20 - year aging ( 2 ppm) aging stability f f pr apr ? ? ? stability f i n p u t v o l t a g e r a n g e f r e q u e n c y s t a b i l i t y ( t e m p , v o l t a g e , a g i n g , e t c ) t o t a l p u l l r a n g e f r e q u e n c y a p r v c _ u v c _ l
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 17 of 36 www.sitime.com dctcxo configuration the dctcxo option offers digital control of the output frequency . the output frequency is controlled by writing frequency control words over the i 2 c interface. there are several advantages of dctcxos relative to vctcxos : 1) frequency co ntrol resolution as low as 5 ppt . this high resolution minimizes accumulated time error in synchronization applications. 2) lower system cost C a vctcxo may need a digit al to analog converter (dac) to drive the control voltage input. in a dctxco, the frequency control is achieved digitally by register writes to the control registers via i 2 c, thereby eliminating the need for a dac. 3) better noise immunity C th e analog signal used to drive the voltage control pin of a vctcxo can be sensitive to noise and the trace over which the signal is routed can be susceptible to noise coupling from the system. the dctcxo does not suffer from analog noise coupling since the frequency c ontr ol is performed digitally through i 2 c. figure 27 . block diagram - dctcxo 4) no frequency pull non - linearity. the frequency pulling is achieved via fractional feedback divider of the pll, eliminating any pull non - linearity conce rn which is typical of quartz based vc tcxos. this improves dynamic performance in closed loop operations. 5) programmable wide pull range C the dctcxo pulling mechanism is via the fractional feedback divider and is therefore not constrained by resonator pulla bility as in quartz based solutions. the SIT5156 offers 16 frequency pull range options from 6.25ppm to 3200ppm, thereby giving system designers great flexibility. figure 28 . top - view - d ctcxo o e / n c 1 2 3 4 5 6 7 8 9 1 0 s c l n c g n d n c n c v d d c l k a 0 s d a
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 18 of 36 www.sitime.com in the dctcxo mode, the device powers up at the nominal operating frequency and pull range specified by the ordering code. after power - up both the pull range and output frequency can be controlled via i 2 c writes to the respective control regist ers. the maximum output frequency change is constrained by the pull range limits. the pull range is specified by the value loaded in the digital pul l range control register. the 1 6 pull range choices are specified in the control register and range from 6. 25ppm to 3200ppm. table 14 below shows the frequency resolution vs. pull range programmed value table 14 . frequency resolution vs. pull range programmed pull range frequency resolution 6.25ppm 5x10 - 12 10ppm 5x10 - 12 12.5 ppm 5 x10 - 12 25ppm 5 x10 - 12 5 0 ppm 5 x10 - 12 80 ppm 5 x10 - 12 100 ppm 5 x10 - 12 120 ppm 5 x10 - 12 1 5 0 ppm 5 x10 - 12 200ppm 5 x10 - 12 400 ppm 1 x10 - 1 1 6 00 ppm 1.4 x10 - 11 800 ppm 2.1 x10 - 11 1200 ppm 3 . 2 x10 - 11 1600 ppm 4.7 x10 - 11 3200 ppm 9 . 4 x10 - 11 the ppm frequency offset i s specified by the 26 bit dcxo frequency control register in two s complement format as described in the i 2 c register descriptions. the power up default value is 00000000000000000000000000b which sets the output frequency at its nominal value (0 ppm). to change the output frequency, a frequency control word is written to 0x00[15:0] (least significant word) and 0x01[9:0] (most significant word). the lsw value should be written first followed by the msw value; the frequency change is initiated after the msw value is written.
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 19 of 36 www.sitime.com figure 29 . pull range and frequency control word
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 20 of 36 www.sitime.com figure 29 shows how the twos complement signed value of the frequency control word sets the output frequency within the ppm pull range set by 0x02:[3:0]. this example shows use of the 200 ppm pull range. therefore to set the desired output frequency, one just needs to calculate the fraction of full scale value ppm, co n vert to twos com plement binary and then write the values to the frequency control registers. the following formula generates the control word value: control word value = rnd((2 25 - 1) * ppm shift from nominal/pull range) , w here rnd is the rounding function which rounds the number to the nearest whole number. two examples follow, assuming the 200 ppm pull range : example 1: ? default o utput frequency = 19.2 mhz ? desired output frequency = 19.201728 mhz (+90 ppm) 2 25 - 1 corresponds to +200 ppm, and the fractional value required for +90 ppm can be calculated as follows . ? 90 ppm / 200 ppm * (2 25 - 1) = 15,099,493.95. rounding to the nearest whole number yields 15,099,494 and converting to two s complement gives a binary value of 111001100110011001100110 and e66666 in hex. example 2: ? default o utput frequency = 10 m hz ? desired output frequency = 9.998 mhz ( - 50 ppm) following the formula shown above, ? ( - 50 ppm / 200 ppm) * (2 25 - 1) = - 8,388,607.75. rounding to the nearest whole number results in - 8,388,608. converting to twos complemen t binary results in 11100000000000000000000000 and 38 00000 in hex. to s ummarize, the procedure for calculating the frequency control word associated with a given ppm offset is as follows: 1) calculate the fraction of the half pull range needed. for example, if the to tal pull range is set for 100 ppm and a +20 ppm shift from the nominal frequency is needed, this fraction is 20 ppm/100 ppm = 0.2 2) multiply this fraction by the full half scale word value, 2 25 - 1 = 33,554,431, round to the nearest whole number and convert the result to twos complement binary. following the +20ppm example, this value is 0.2 * 33,554,431 = 6,710,886.2 and rounded to 6,710,886. 3) write the twos complement binary value starting with the least significant word (lsw) 0x00[16:0], followed by the most significant word (msw), 0x01[9:0]. if the user desires that the output remains enabled while changing the frequency, a 1 must also be written to the oe control bit 0x01[10] if the device has software oe control enabled. it is important to note that the maximum dig ital control update rate is 38 k hz regardless of i 2 c bus speed.
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 21 of 36 www.sitime.com i 2 c control registers the dctcxo option enables control of frequency pull range, frequency pull value, output enable and d rive strength control via i 2 c writes to t he control registers. table 15 below shows the register map summary and the detailed register descriptions follow. table 15 . register map summary address bits access description 0x00 [15:0] rw digital fre quency control least significant word (lsw) 0x01 [15:11] r not used [10] rw oe control. this bit is only active if the output enable function is under software control. if the device is configur ed for hardware control using the oe pin, writing to this b it has no effect. [9:0] rw digital frequency co ntrol most significa nt word (msw) 0x02 [15:4] r not used [3:0] rw digital pull range c ontrol 0x05 [15:4] r not used [3:0] rw pull - up drive strength co ntrol 0x06 [15:4] r not used [3:0] rw pull - down drive strength contr ol register descriptions register address: 0x0 0. digital frequency control least significant word (lsw) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 name digital frequency co ntrol least signific ant word (lsw) [15:0] bits name access description 15:0 digital frequency control least significant word rw bits [15:0] are the lower 16 bits of the 26 bit frequencycontrolword and are the least sign ificant word (lsw). the upper 10 bits are in regsiter 0x01[9:0] and are the m o st significant word (msw). the lower 16 bits together with the upper 10 bits specify a 26 - bit frequency control word. this power - up default values of all 26 bits are 0 which se ts the output frequency at its nominal value. after power - up, the system can write to these two registers to pull the frequency across the pull ra nge. the register values are twos complement to support positive and negative control values. the lsw value s hould be written before the msw value because the frequency change is initiated when the new values are loaded into the msw. more details and examples are discussed in the next section.
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 22 of 36 www.sitime.com register address: 0x01. oe control, digital frequency control m ost significant word (msw) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access r r r r r rw rw rw rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 name not used oe dcxo frequency control[9:0] msw bits name access description 15:11 not use d r bits [15:10] are read only and return all 0s when read. writing to these bits has no effect. 10 oe control rw output enable software control. allows the user to enable and disable the output driver via i 2 c. 0 = output disabled (default) 1 = output en abled this bit is only active if the output e nable function is under software control. if the device is configured for hardware control using the oe pin, writing to this bit has no effect. 9:0 digital frequency co ntrol most significant wor d (msw) rw bits [9:0] are the upper 10 bits of the 26 bit frequen cycontrol word and are the most significant word (msw). the lower 16 bits are in registe r 0x00[15:0] and are the least s i gnificant word (lsw). these lower 16 bits together with the upper 10 bits specify a 26 - bit frequency control word. this power - up default values of all 26 bits are 0 which sets the output frequency at its nominal value. after power - up, the system can write to these two registers to pull the frequency across the pull range. the register value s are two s complement to support positive and negative control values. the lsw value should be written before the msw value because the frequency change is in itiated when the new values are loaded into the msw. more details and examples are discussed in t he next section.
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 23 of 36 www.sitime.com register address: 0x02. digital pull range control [ 7 ] bit 15 14 13 12 11 10 9 6 5 6 5 4 3 2 1 0 access r r r r r r r r r r r r rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 x x x x name none digital pull range control notes: 7. default values are factory set but can be over - written after power - up. bits name access description 15:4 none r bits [15:4] are read only and return all 0s when read. writing to these bits has no effect. 3:0 digita l pull range control rw sets the digital pull range of the dcxo. the table below shows the available pull range values and associated bit settings. the default value is factory programmed bit 3 2 1 0 0 0 0 0: 6.25ppm 0 0 0 1: 10ppm 0 0 1 0: 12.5ppm 0 0 1 1: 25ppm 0 1 0 0: 50ppm 0 1 0 1: 80ppm 0 1 1 0: 100ppm 0 1 1 1: 125ppm 1 0 0 0: 150ppm 1 0 0 1: 200ppm 1 0 1 0: 400ppm 1 0 1 1: 600ppm 1 1 0 0: 800ppm 1 1 0 1: 1200ppm 1 1 1 0: 1600ppm 1 1 1 1: 3200ppm
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 24 of 36 www.sitime.com register address: 0x05. pull - up drive strength control bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access r r r r r r r r r r r r rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 name none pull - up drive strength control bits name access description 15:4 none r bits [15:4] are rea d only and return all 0s when read. writing to these bits has no effect. 3:0 pull - up drive strength control rw sets the pull - up drive strength of the output driver. the below table shows the range of values. bit 3 2 1 0 0 0 0 0: 5x (default) 0 0 0 1: 6x 0 0 1 0: 7x 0 0 1 1: 8x 0 1 0 0: 9x 0 1 0 1: 10x 0 1 1 0: 11x 0 1 1 1: 12x 1 0 0 0: 13x 1 0 0 1: 14x 1 0 1 0: 15x 1 0 1 1: 16x 1 1 0 0: 17x 1 1 0 1: 18x 1 1 1 0: 19x 1 1 1 1: 20x
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 25 of 36 www.sitime.com register address: 0x06. pull - down drive strength control bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access r r r r r r r r r r r r rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 name none pull - down drive strength control bits name access description 5:4 none r bits [15:4] are read only and return all 0s when re ad. writing to these bits has no effect. 3:0 pull - down drive strength control rw sets the pull - down drive strength of the output driver. the below table shows the range of values. bit 3 2 1 0 0 0 0 0: 5x (default) 0 0 0 1: 6x 0 0 1 0: 7x 0 0 1 1: 8x 0 1 0 0: 9x 0 1 0 1: 10x 0 1 1 0: 11x 0 1 1 1: 12x 1 0 0 0: 13x 1 0 0 1: 14x 1 0 1 0: 15x 1 0 1 1: 16x 1 1 0 0: 17x 1 1 0 1: 18x 1 1 1 0: 19x 1 1 1 1: 20x
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 26 of 36 www.sitime.com serial interface configuration description the SIT5156 may be ordered with the i 2 c interface to access registers which control the dctcxo frequency pull range, frequency pull value, and output drive strength. the SIT5156 i 2 c slave only interface supports clock speeds up to 1 mhz. the SIT5156 i 2 c module is based on the i 2 c specification, um1024 (rev.6 april 4, 2014 of nxp semiconductor ) . serial signal format the sda line must be stable during the high period of the scl. sda transitions are allowed only during scl low level for data communication. only one transition is allowed during the low scl state to communicate one bit of data. figure 30 shows t he detailed timing diagram. the idle i 2 c bus state occurs when both scl and sda are not being driven by any master and are therefore in a logic hi state due to the pull up resistors. every transaction begins with a start (s) signal and ends with a stop (p) signal. a start condition is defined by a high to low transition on the sda while scl is high. a stop condition is defined by a low to high transition on the sda while scl is high. start and stop conditions are always generated by the master. this slave module also supports repeated start (sr) condition which is same as start condition instead of stop condition (blue color line shows repeated start in figure 31 ). figure 30 . data and clock timing relation in i 2 c bus figure 31 . start and stop (or repeated start) condi tion s d a s c l d a t a l i n e s t a b l e : d a t a v a l i d c h a n g e o f d a t a a l l o w e d s e t u p t i m e s d a s c l s p s t a r t c o n d i t i o n s t o p c o n d i t i o n h o l d t i m e s e t u p t i m e h o l d t i m e
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 27 of 36 www.sitime.com parallel signal format every data byte is eight bits long. the number of bytes that can be transmitted per transfer is unrestricted. data is transferred with the msb (most significant bit) first. the detailed data transfer format is shown in figure 33 b elow. the acknowledge bit must occur after every byte transfer and it allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. the acknowledge signal is defined as follows: the transmitter releases the sda line during the acknowledge clock pulse so the receiver can pull the sda line low and it remains stable low during the high period of this clock pulse. setup and hold times must also be taken into acc ount. when sda remains high during this ninth clock pulse, this is defined as the not - acknowledge signal (nack). the master can then generate either a stop condition to abort the transfer, or a repeated start condition to start a new transfer. the only con dition that leads to the generation of nack from the SIT5156 is when the transmitted address does not match the slave address. when the master is reading data from the SIT5156 , the SIT5156 expects the ack from the master at the end of received data, so tha t the slave releases the sda line and the master can generate the stop or repeated start. if there is a nack signal at the end of the data, then the SIT5156 tries to send the next data. if the first bit of the next data is 0, then the SIT5156 holds the s da line to 0, thereby blocking the master from generating a stop/(re)start signal. parallel data format this i 2 c slave module supports 7 - bit device addressing format. the 8 th bit is a read/write bit and 0 indicates a read transaction and a 1 indicat es a write transaction. the register addresses are 8 - bits long with an address range of 0 to 255 (00h to ffh). auto address incrementing is supported which allows data to be transferred to contiguous addresses without the need to write each address beyond the first address. since the maximum register address value is 255, t he address will roll from 255 back to 0 when auto address incrementing is used. obviously, auto address incrementing should only be used for writing to contiguous addresses. the data form at is 16 - bit (two bytes) with the most significant byte being transferred first. figure 32 . parallel signaling format figure 33 . parallel data byt e format s d a s c l s o r s r p o r s r s t a r t c o n d i t i o n s t o p c o n d i t i o n m s b 1 2 7 8 9 a c k 1 2 3 t o 8 a c k n o w l e d g e f r o m s l a v e 9 a c k a c k n o w l e d g e f r o m r e c e i v e r s d a s c l s p s t a r t c o n d i t i o n s t o p c o n d i t i o n 8 9 1 t o 7 9 1 t o 8 9 1 t o 8 s l a v e a d d r e s s w / r a c k a c k a c k d a t a - m s b r e g i s t e r a d d r e s s 9 1 t o 8 a c k d a t a - l s b
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 28 of 36 www.sitime.com figure 3 4 below shows the i 2 c sequence for writing the 4 - byte control word using auto address incrementing. figure 34 . writing the frequency control word table 16 . dc tc xo delay and settling time parameter symbol minimum typical maximum units notes frequency change delay t fdelay C 22 C sec frequency settling time t settle C 30 C sec time to settle to 1% of final frequency value s t o p c o n d i t i o n o u t p u t f r e q u e n c y f 0 t f d e l a y t s e t t l e f 0 + f 1 0 . 5 % s t d _ a d d r e s s [ 6 : 0 ] w a r _ a d d r e s s [ 7 : 0 ] = 0 0 a 0 x 0 0 [ 1 5 : 8 ] a 0 x 0 0 [ 7 : 0 ] a d i g i t a l f r e q u e n c y c o n t r o l C l e a s t s i g n i f i c a n t w o r d ( l s w ) [ 1 5 : 0 ] x x x x x o e 0 x 0 1 [ 1 5 : 8 ] a m s w [ 7 : 0 ] a s p d i g i t a l f r e q u e n c y c o n t r o l C m o s t s i g n i f i c a n t w o r d ( m s w ) [ 9 : 0 ] l s w [ 1 5 : 8 ] l s w [ 7 : 0 ] 0 x 0 1 [ 7 : 0 ] 9 8 s l a v e d r i v e s b i t ( s ) o n b u s m a s t e r d r i v e s b i t ( s ) o n b u s s t s t a r t s p s t o p w w r i t e r r e a d a a c k n o w l e d g e o e o u t p u t e n a b l e x d o n t c a r e r e g i s t e r b i t n o t u s e d .
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 29 of 36 www.sitime.com i 2 c timing specification the below timing diagram and table illustrate the timing relationships for both master and slave. figure 35 . i 2 c timing diagram table 17 . i 2 c timing requirements parameter speed mode value unit t setup fm + (1 mhz) > 50 nsec fm (400khz) > 100 nsec sm (100khz) > 250 nsec t hold fm+ (1 mhz) > 0 nsec fm (400khz) > 0 nsec sm (100khz) > 0 nsec t vd:awk fm+ > 450 nsec fm (400khz) > 900 nsec sm (100khz) > 3450 nsec t vd:dat na (s - awk + s - data)/(m - awk/ s - data) master spec both ( slave/master) spec
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 30 of 36 www.sitime.com i 2 c device address modes there are two i 2 c a ddress modes: 1) factory programmed mode. the lower 4 bits of the 7 - bit device address are set by ordering code as shown in table 18 below. there are 16 fact ory programmed addresses available. in this mode, pin 5 is n c and the a 0 i 2 c address pin control function is not available. 2) a0 p in control. this mode allows the user to select between two i 2 c device addresses as shown in table 19 . table 18 . factory programmed i 2 c address control [ 8 ] i 2 c address ordering code device i 2 c address 0 1100000 1 1100001 2 1100010 3 1100011 4 1100100 5 1100101 6 1100110 7 1100111 8 1101000 9 1101001 a 1101010 b 1101011 c 1101100 d 1101101 e 1101110 f 1101111 notes : 8. table 1 8 is only valid for the dctc xo device option which supports i 2 c control . table 19 . pin selectable i 2 c address control [ 9 ] a0 pin 5 i 2 c address 0 1100010 1 1101010 notes: 9. table 19 is only valid for the dctcxo device option which supports i 2 c control and a0 device address control pin.
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 31 of 36 www.sitime.com sche matic example figure 36 . schematic example - dctcxo
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 32 of 36 www.sitime.com dimensions and patterns package size C dimensions (unit: mm) recommend ed land pattern (unit: mm)
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 33 of 36 www.sitime.com layout guidelines ? SIT5156 uses internal regulators to minimize the impact of the power supply noise. for further reduction of noise, it is essential to use two bypass capacitors (0.1 f and 10 f). place the bypass capacitors as close to the vdd as possible, typically within 1 to 2 mm. ensure that the 0.1uf cap is the clo sest to the device vdd and gnd power pins ? it is also recommended to connect all nc pins to the ground plane and place multiple vias under the gnd pin for maximum heat dissipation. ? for additional layout recommendations, refer to the best design layout practices . manufacturing guidelines the SIT5156 super - tcxos is a precision timing device. proper pcb solder and cleaning process must be followed in order to en sure best performance and long - term reliability. ? no ultrasonic or megasonic cleaning: do not subject the SIT5156 to an ultrasonic or megasonic cleaning environment. permanent damage or long - term reliability issues to the device may occur in such an event. ? no external cover. unlike legacy quartz tcxos, the SIT5156 is engineered to operate reliably without performance degradation, in the presence of ambient disturbers such as airflow and sudden temperature c hanges. therefore, the use of an external cover typ ical of quartz tcxos is not needed. ? reflow profile: for mounting these devices to the pcb, ipc/jedec j - std - 020 compliant reflow profile must be used. device performance is not guaranteed if soldered manually or with a non - compliant reflow profile. ? pcb cle aning: after the surface mount (smt)/reflow process, solder flux residues may be present on the pcb and around the pads of the device. excess residual solder flux may lead to problems such as pad corrosion, elevate leakage currents, increased frequency agi ng, or other performance degradation. for optimal device performance and long - term reliability, thorough cleaning and drying of the pcb is required as shortly after the reflow process as possible, even when using a no clean flux. care should be taken to remove all residual flux between the sitime device and the pcb. note that ultrasonic pcb cleaning should not be used with sitime oscillators. ? for additional manufacturing guidelines and marking/ tape - reel instructions, refer to sitime manufacturing notes .
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 34 of 36 www.sitime.com ordering information the part no. guide is for reference only. to customize and build an exact part number, use the sitime part number generator . use the part number decoder to validate the part number. refer to table 20 for o rdering c ode combinations regarding device configuration , pin 1 fu nctionality and i 2 c addres s mode. notes: 10. - corresponds to the default rise/fall time for lvcmos output as specified in table 1 (electrical chara cteristics). contact sitime for other rise/fall time options for best emi. 11. bulk is available for sampling only 12. 0 is selected when the device is configured as a tc xo (pin 1 = e or n). t to u are applicable in vctcxo mode (pin 1 = v) and dctcxo mode (pin 1 = e or n) s i t 5 1 5 6 a c - f k - 3 3 v q 1 9 . 1 2 3 4 5 6 t p a r t f a m i l y r e v i s i o n l e t t e r a i s t h e r e v i s i o n o f s i l i c o n p a c k a g e s i z e f r e q u e n c y s t a b i l i t y 3 k : f o r 0 . 5 p p m a : d : o u t p u t w a v e f o r m [ 1 0 ] - : l v c m o s c : c l i p p e d s i n e w a v e d e v i c e o p t i o n / f e a t u r e p i n 1 f : 5 . 0 x 3 . 2 m m v : v c t c x o , p i n 1 v o l t a g e c o n t r o l e : t c x o , p i n 1 o u t p u t e n a b l e n : t c x o , p i n 1 n o c o n n e c t i : d c t c x o w i t h i 2 c c o n t r o l , p i n 1 o e j : d c t c x o w i t h i 2 c c o n t r o l , p i n 1 n c , s o f t w a r e o e c o n t r o l p u l l r a n g e v o l t a g e s u p p l y 2 5 : 2 . 5 v 1 0 % 2 8 : 2 . 8 v 1 0 % 3 0 : 3 . 0 v 1 0 % 3 3 : 3 . 3 v 1 0 % 0 : f i x e d f r e q u e n c y f o r t c x o t : 6 . 2 5 p p m v c t c x o , q : 1 2 . 5 p p m v c t c x o , d c t c x o m : 2 5 p p m v c t c x o , d c t c x o b : 5 0 p p m v c t c x o , d c t c x o c : 8 0 p p m v c t c x o , d c t c x o e : 1 0 0 p p m v c t c x o , d c t c x o g : 1 5 0 p p m v c t c x o , d c t c x o h : 2 0 0 p p m v c t c x o , d c t c x o x : 4 0 0 p p m v c t c x o , d c t c x o y : 8 0 0 p p m v c t c x o , d c t c x o z : 1 6 0 0 p p m v c t c x o , d c t c x o u : 3 2 0 0 p p m v c t c x o , d c t c x o v a l u e s : - , 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , a , b , c , d , e , f , g - : i 2 c n o t u s e d ( t c x o , v c t c x o ) 0 - f : i 2 c a d d r e s s f a c t o r y p r o g r a m m e d s e t s b i t s 3 : 0 o f d e v i c e i 2 c a d d r e s s t o t h e h e x v a l u e o f t h e o r d e r i n g c o d e . w h e n t h e i 2 c a d d r e s s i s f a c t o r y p r o g r a m m e d u s i n g t h e s e c o d e s , p i n a 0 i s n c g : i 2 c a d d r e s s c o n t r o l l e d b y a 0 p i n i 2 c a d d r e s s m o d e & o r d e r i n g c o d e s d c t c x o o n l y s i t 5 1 5 6 f o r 1 . 0 p p m f o r 2 . 5 p p m [ 1 1 ] 1 0 p p m r : d c t c x o d c t c x o 1 2 5 p p m f : d c t c x o v c t c x o , v c t c x o , 6 0 0 p p m l : d c t c x o v c t c x o , 1 2 0 0 p p m s : d c t c x o v c t c x o , - [ 1 2 ] f r e q u e n c y 1 . 0 0 0 0 0 0 t o 6 0 . 0 0 0 0 0 0 m h z , l v c m o s 1 . 0 0 0 0 0 0 t o 5 0 . 0 0 0 0 0 0 m h z , c l i p p e d s i n e w a v e t e m p e r a t u r e r a n g e e : e x t e n d e d i n d u s t r i a l , - 4 0 t o 1 0 5 c c : e x t e n d e d c o m m e r c i a l , - 2 0 t o 7 0 c i : i n d u s t r i a l , - 4 0 t o 8 5 c
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 35 of 36 www.sitime.com table 20 . ordering codes for device configuration vs. feature pin 1 and i 2 c address mode device configuration feature pin 1 i 2 c address mode tcxo e : pin 1 output enable n : pin 1 no connect C vctcxo v : pin 1 voltage con trol C dctcxo i : pin 1 output enable j : pin 1 no connect, output enable under software control 0 - f: factory programmed i 2 c address g: i 2 c address controlled by a0 pin table 21 . ordering codes for supported tape & reel pac king method device size (mm x mm) 16 mm t&r(3ku) 16 mm t&r(1ku) 12 mm t&r(3ku) 12 mm t&r(1ku) 8 mm t&r(3ku) 8 mm t&r(1ku) 5 .0 x 3.2 C C t y C C
sit51 56 1 to 60 mhz , 0.5 ppm elite platform? super - tcxo preliminary rev 0.60 page 36 of 36 www.sitime.com table 22 . additional information d ocument description download link time machine ii mems oscillator programmer http://www.sitime.com/support/time - machine - oscillator - programmer field programmable oscillators devices that can be programmable in the field by time machine ii http://www.sitime.com/products/field - programmable - oscillators manufacturing notes tape & reel dimension, reflow profile and other manufacturing related info http://www.sitime.com/manufacturing - notes qualification reports rohs report, reliability reports, composition reports http://www.sitime.com/support/quality - and - reliability performa nce reports additional performance data such as phase noise, current consumption and jitter for selected frequencies ht tp:// www.sitime.com/support/performance - measurement - report termination techniques termination design recommendations http://www.sitime.com/support/application - notes layout techniques layout recommendations http://www.sitime.com/support/application - notes table 23 . revision history version release date change summary 0.1 0 5/10/ 2016 first r elease , advanced information 0.15 0 8/ 0 4/2016 replaced qfn package with soic - 8 package add ed 10 f bypass cap requirement updated test circuits to reflect both new bypass cap requiremen t and soic - 8 package update t able 1 (electrical characteri stics) 0.16 0 9/12/2016 updated test circuit diagrams 0.2 0 9/21/2016 revised table 1 (electrical characteristics) 0.4 12/19/2016 added dctcxo mode added i2c information added i2c 0.5 07/21/2017 added 5.0x3.2 mm package information updated table 1: elec trical characteristics 0.51 08/20/ 2017 changed to preliminary updated 5.0x3.2 mm package dimensions updated test cir c uits updated table 1 (electrical characteristics) updated part ordering info misc. corrections 0.52 11/27/2017 updated the t hermal c harac teristics table added more on m anufacturing g uideline section 0.55 02/05/2018 added view labels to p ackage d rawing s updated the freq vs. output type changes to 60 mhz updated links and notes 0 .60 03/01/2018 added 105 c support , updated ordering information sitime corporation , 5451 patrick henry drive , santa c lara , ca 95054 , usa | phone: + 1 - 408 - 328 - 4400 | fax: +1 - 408 - 328 - 4439 ? sitime corporation 2016 - 201 8 . the information contained herein is subject to change at any time without notice. sitime assumes no responsibility or liabi lity for any loss, damage or defe ct of a product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a sitime produc t, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have b een soldered or alte red during assembly and are not capable of being tested by sitime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, the rmal, o r electrical stress. disclaimer: sitime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and al l express or implied warranties, either in fact or by operation of law, statutory or otherwise, i ncluding the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or usage of trade, as well as any common - law duties relating to accuracy or lack of negligence, with res pect to this material, any sitime product and any product documentation. products sold by sitime are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications wh ere human life may be involved or at stake. all sales are made conditioned upon compliance with the critical uses policy set forth below. critical use exclusion policy buyer agrees not to use sitime's products for any application or in any components used in life support devices or to operate nuclear facilities or for use in other mission - critical applications or components where human life or property may be at stake. sitime owns all rights, title and interest to the intellectual property related to siti me's products, including any software, firmware, copyright, patent, or trademark. the sale of sitime products does not convey or imply any license under patent or other rights. sitime retains the copyright and trademark rights in all documents, catalogs an d plans supplied pursuant to or ancillary to the sale of products or services by sitime. unless otherwise agreed to in writing by sitime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibi ted.

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